Low Power 4-Bit Ripple Carry Adder using the GDI Technique

M. Taneja, V. Mukala, and S. Muthukumar (India)

Keywords

GDI (Gate Diffusion-Input), CMOS, 0.18µm technology, PTL (Pass Transistor Logic), full adder, Twin well and P well Process.

Abstract

An efficient implementation of 4-bit adder using Gate Diffusion-Input (GDI) technique is presented. GDI is a new technique of low power digital combinational circuit design. This technique allows reducing the amount of area, power consumption, propagation delay of the digital circuits while maintaining low complexity of logic design. Performance comparison with CMOS technology is presented with respect to number of devices, delay and power dissipation using 0.18µm technology. Properties of implemented circuit are discussed and simulation is done using Cadence ADE and the results are reported.

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