Intellectual Property (IP) Cores and a Logic Fault Test Simulation Environment

M.H. Assaf, L.-A. Moore (Trinidad and Tobago), S.R. Das (Canada, USA), S.N. Biswas, A.R. Applegate (USA), and E.M. Petriu (Canada)

Keywords

Application-specific integrated circuits (ASICs), automatic test pattern generator (ATPG), built-in selftesting (BIST), intellectual property (IP) core, output response analyzer (ORA), stuck-at fault model.

Abstract

The subject paper develops a low-level logic fault test simulation environment for embedded systems targeted specifically towards application-specific integrated circuits (ASICs) and intellectual property (IP) cores. The simulation architecture emulates a typical built-in self testing (BIST) environment with automatic test pattern generator (ATPG) that sends its outputs to a circuit (core) under test (CUT) and the output streams from the CUT are fed into an output response analyzer (ORA). The paper describes in detail the test architecture environment, test application and fault injection including the application of the logic fault simulator. Results on simulation on some specific IP cores designed using combinations from ISCAS 85 combinational and ISCAS 89 sequential benchmark circuits are provided as well for appraisal.

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