A Low-Power Fault-Tolerant NoC using Error Correction and Detection Codes

Y. Kojima, H. Matsutani, M. Koibuchi, and H. Amano (Japan)

Keywords

Network-on-Chip, fault tolerance, soft error, power consumption

Abstract

Power consumption and reliability become two crucial factors in designing Network-on-Chip (NoC) for modern chip multiprocessors. In this paper, we present a low power fault-tolerant NoC architecture by using error correction and detection codes in order to reduce the supply voltage, while the bit error rate of the end-to-end on-chip communication is maintained. The method aims to optimize the power consumption of a given NoC by selecting the best fault-tolerant technique. Simulation results show that our error detection/correction techniques greatly reduce the number of re-transmitted packets due to soft errors. These techniques also reduce up to 40% of flit transmission energy compared to the original NoC without any fault-tolerant techniques. We show that control information of each packet (e.g., destination address) should be protected first by using a high-reliable error detection or correction technique when the error rate is high.

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