Implementation of a Singular Value Decomposition Module on an FPGA

Masoud Hosseinimehr and Norma Montealegre

Keywords

Singular Value Decomposition, Field Programmable Gate Array

Abstract

Since FPGAs are more flexible than general purpose processors, they are used for accelerating the computation of algorithms. Singular value decomposition is the factorization of a matrix, useful in computations executed for signal processing and pattern recognition. This paper deals with the hardware implementation of the singular value decomposition of a given matrix. The used algorithm is based on a compact SVD presented by A. O. Tarakanov. That algorithm compared with others showed to be resource efficient and straightforward for being implemented in hardware. It has been programmed in VHDL and implemented in an FPGA trying to find a compromise among resources, run time, precision and parallelism. The VHDL module uses floating point numbers which bit width can be modified for tuning the precision of the results. Conventional higher level languages for the development of hardware do not allow working with floating point numbers and give rather a less optimal design as the evaluation at the end shows.

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