Design and VLSI Implementation of Modified AES with Neural Networks for Image Coding

Kanakatte A. Dattathreya

Keywords

Information security, encryption, decryption, FPGA, VLSI Design, image compression

Abstract

This paper is an attempt to address the security issue while transmitting the images over channel in an unprotected environment. Artificial neural networks have been used for image compression and AES is used for data encryption of compressed images. The feed forward network adopted compression of image up to a 97% and thus reducing the complexity in AES encryption. The compressor and encryption is modeled using HDL and synthesized using Xilinx ISE targeting Virtex2 and Virtex5 FPGA. The design consumes 9% of the slices and 1.128 W of power. The developed design is reconfigurable and hence used for real time applications.

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