VLSI Architecture Design for BNN Speech Recognition

J.-C. Wang, J.-F. Wang, and F.-M. Li (Taiwan)


VLSI, speech recognition, Bayesian neural network.


In this paper, we present the efficient VLSI architecture for the stand-alone application of the speech recognition system based on Bayesian neural network (BNN). Consider the recognition phase, the architecture of the Bayesian distance unit (BDU) is constructed based on one or multiple fundamental distance units. Template-serial and template parallel architectures are both proposed to be associated with the BDU to perform the recognition procedure. In accordance with the number of the basic recognition units and the adopted BDU architecture, the choice is made between template-serial and template-parallel architectures so that the frame synchronous feature can be achieved in an efficient way.

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