K. Rauma, O. Laakkonen, K. Szmich, J. Luukko, and O. Pyrhönen (Finland)
Simulation, Simulation tools, HDL, Programmable logic
Field programmable gate arrays have developed rapidly in
last years. The size and the speed of the circuits has
grown. The devices combine the flexibility of software
with the performance of hardware giving increased
efficiency. This offers an opportunity to implement larger
models that also includes a lot of arithmetic operations.
Larger models are more difficult to test and verificate.
This paper presents a new way to simulate and verificate
HDL based designs in Simulink1
using a new tool called
HDL simulation library. An arithmetic approach of direct
torque control (DTC) algorithms was implemented in
FPGA. The whole DTC-model was tested in Simulink
using a full motor model created in it. The simulation and
verification of DTC model and benefits of the HDL
simulation library are described here.