A 2D Forward/Inverse Architecture for 4x4 ICT Transform of H.264 Oriented to FPGA

A.M. Patiño (Mexico), M.M. Peiró, and F.J. Ballester (Spain)

Keywords

ICT, H.264, FPGA, VLSI

Abstract

In this work we propose a new architecture for the implementation on FPGA of the 4x4 Bi-dimensional Integer Cosine Transform (ICT), the transformation adopted in the H.264 standard. The area and speed synthesis results are shown and the comparison reveals that the architecture occupies the lowest area reaching 487fps on 4:2:0 HD (1280x720p) video formats.

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