Implementing Hardware Multithreading in a VLIW Architecture

S. Suijkerbuijk and B.H.H. Juurlink (The Netherlands)

Keywords

VLIW processor, multithreading, block interleaving, Tri Media.

Abstract

Hardware multithreading is a well-known technique to in crease the utilization of processor resources. However, most studies have focused on superscalar processor organi zations. This paper analyzes which type of hardware mul tithreading is most suitable for a VLIW architecture and proposes two buffers to increase the ef´Čüciency of hardware multithreading. An important goal of our work is that no software changes should be necessary so that legacy code can be executed without change. In order to achieve this we show that there must be a maximum amount of time a hardware thread may be active. The experimental results show that the implemented technique attains a maximum speedup of 27% compared to the single-threaded VLIW processor.

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