A Custom Designed Image Processing Microcomputer with Parallel DSPs and Dynamically Reconfigurable Hardware

C.W. Murphy and D.M. Harvey (UK)

Keywords

Image Manipulation and Compression, Visual Inspection, Dynamically reconfigurable Field Programmable Gate Arrays (FPGAs), Run-timereconfigurable (RTR), Parallel Digital Signal Processors (DSPs), Binary Discrete Cosine Transform(BinDCT).

Abstract

This paper outlines a parallel processing system designed specifically to prototype novel image processing hardware and software architectures. Using an existing Texas Instruments TMS320C40 DSP TIM 40 standard parallel processor as the base architecture, Xilinx XC6200 dynamic configurable FPGAs have been inserted to provide run-time reconfigurable hardware resources. Through use of this architecture novel image processing applications have been demonstrated. An outcome of this work has been the development of run-time reconfigurable BinDCT algorithm coprocessors. These have demonstrated how loss-less compression and operand throughput can be improved through using dynamic compared to static hardware implementations.

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