Dynamic Configurable DSP Parallel Processing Architecture

C.W. Murphy, D.M. Harvey, and L.J. Nicolson (UK)


Reconfigurable computing, virtual hardware, parallel processing, dynamic coprocessor, run time reconfiguration, adaptive routing hub.


This paper describes the realisation of a dynamic hardware capability within a Texas Instruments TMS320C40 parallel processing environment. To conduct this task a custom designed Xilinx XC6200 FPGA family development system has been constructed. This has facilitated the development of dynamic coprocessor and routing hub hardware within the DSP architecture. This run-time reconfigurable parallel processing system has been applied to a range of applications including image processing front-end and novel DCT compression methods.

Important Links:

Go Back