Efficient Parallel VLSI Traffic Schedulers for ATM Systems

S. Dilis, G. Doumenis, G. Konstantoulakis, G. Korinthios, D. Reisis, and G. Synnefakis (Greece)

Keywords

ATM, QoS, parallel architectures, traffic scheduling, traffic shaping.

Abstract

The performance of a traffic shaper plays an important role in the overall performance of an ATM system because of the limitation that it imposes to the bandwidth allocation. An efficient scheduling process results in the improvement of the system’s performance. This paper presents four techniques, which enhance the performance of the traffic scheduling processes for ATM systems. The shaper uses a parallel calendar-based VLSI architecture to speed up the processes of searching, computing priorities and updating pointers. Each organization involves processing elements able to perform simple instructions and interconnected through a low cost interconnection scheme. The number of elements is proportional to the number k of priorities related to the traffic profiles of the ATM connections. Each organization presents an efficient solution to the problem of speeding up the computing the time-slots for transmitting ATM cells while keeping the required VLSI area small as well as simplifying the control. As a result, the fastest of the four organizations uses k processing elements and lists and it can compute a time-slot in log2k steps as compared to the sequential calendar algorithm, which takes an arbitrary long number of steps for this computation. The entire system constitutes a component, which can efficiently accommodate either a switch or an intelligent buffer.

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