T. Abe, K. Iwai, T. Morimura, R. Ogawa, K. Yasufuku, and H. Amano (Japan)
: processor, cache, static scheduling, multi
grain parallelism, parallel computing system
Multi-grain parallelizing scheme is one of effective par
allelizing schemes which exploits various level paral
lelism: coarse-grain(macro-dataﬂow), medium-grain(loop
level parallelizing) and near-ﬁne-grain(statements paral
lelizing) from a sequential program. A multi-processor
ASCA is designed for efﬁcient execution of multi-grain
A processing element called MAPLE are mainly de
signed for near-ﬁne-grain parallelism, and has two mod
ules called MAPLE core and DTC. The MAPLE core is a
simple RISC processor which executes every operation in
a ﬁxed time and realize direct register to register transfer.
The DTC realize a software controlled cache by instruc
tions which are generated by the compiler. With a static
scheduling, near-ﬁne-grain parallel processing is efﬁciently
performed using a communication mechanism with receive
registers, and non-synchronization operation mechanism.
Through implementation of the prototype chip and
clock level simulation, it appears that the performance of
a single chip multi-processor with 4 MAPLEs is close to
those of modern super-scaler processors in spite of small
hardware and low clock frequency.