Enhancing Compression and Encryption of Image with FPGA-based Cryptosystems

H.-C. Ke, S.-C. Ou, K.-W. Jwo, and W.-T. Sung (Taiwan)

Keywords

:Discrete Wavelet Transform (DWT), Significance-Linked Connected Component Analysis (SLCCA), Advance Encryption Standard (AES), Image Compression Encryption Scheme (ICES).

Abstract

Compression and Encryption technologies are now such an important area that would seem efficiently to overcome network bandwidth and security issues. We present a novel scheme namely Image Compression Encryption Scheme (ICES), which combines Discrete Wavelet Transform (DWT), Significance-Linked Connected Component Analysis (SLCCA), and Advance Encryption Standard (AES). Through ICES, it can efficiently reduce overall processing time. In this paper, we have developed a hardware system to real-time compress and encrypt image through image compression encryption scheme. The system exploits parallel processing to improve the throughout of the cryptosystem for Internet multimedia applications to implement the ICES. Using hardware acceleration for encryption and decryption, we can make use of FPGA implementation of DWT, SLCCA and AES algorithm. With the aid of a pipeline structure a very high data throughput of 330Mbit/s at a clock frequency of 40MHz was achieved. Therefore the ICES are secure, fast, and suitable for high speed network protocols like ATM (Asynchronous Transfer Mode), FDDI (Fiber Distributed Data Interface) or Internet multimedia applications.

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