Performance Evaluation on Low-Latency Communication Mechanism of DIMMnet-2

A. Kitamura, Y. Miyabe, T. Miyashiro, N. Tanabe, H. Nakajo, and H. Amano (Japan)

Keywords

PC Cluster, Memory Slot, Interconnect

Abstract

By recent performance improvement of interconnection networks for PC cluster, a standard I/O bus which con nects network interface becomes the performance bottle neck. DIMMnet is a network interface which can solve the problem by using the memory bus instead of PCI bus or other I/O buses. The second generation network in terface DIMMnet-2 can be connected with DDR-SDRAM slot. Although the current board is a prototype using an FPGA, using BOTF which is low latency PIO communi cation method, the bidirectional bandwidth reaches about 1087.56 MByte/s, and the minimum unidirectional latency is about 0.632 ┬Ás.

Important Links:



Go Back