Modeling and Evaluation of the Interconnection-driven Repairability for Distributed Embedded Memory Cores on Chip

B. Jang, N. Park, K.M. George, and G.E. Hedrick (USA)


Modeling, Memory repair, System-on-Chip (SoC), Reconfiguration


Test-and-repair process is one of the most critical issues for the success of SoC (System-on-Chip) design. More reliable and dependable SoC design with built-in self test/diagnosis/repair is desirable more than in traditional ASIC (Application Specific Integrated Circuit) or MCM (Multichip Module) design. It is forecast by ITRS (International Technology Roadmap in Semiconductor) that memory cores will be dominant in SoC area and tend to be distributed into small available spaces left after placing logic cores and others into the SoC area. This opens up a new concept of memory test and repair. In this paper, distributed memory interconnection topology is considered as a method for obtaining higher reliability of memory cores in SoC. An effective memory repair method by using the proposed spare line borrowing (software-driven reconfiguration) technique is investigated. The effect of interconnection topology on the reliability of distributed memory cores is analyzed through modeling and extensive parametric simulation.

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