JBits Implementation and Design Verification in Space Compressor Design of Digital Circuits

M.H. Assaf, R.R. Abielmona, P. Abolghasem, S.R. Das, E.M. Petriu, and V. Groza (Canada)


JBits implementation, space compression, system-on-a-chip, BIST, zero-aliasing compaction, digital circuits.


This paper proposes a design architecture to verify the concept of a zero-aliasing space compaction model suitable for built-in self-testing ( BIST ) of digital cores by using a reconfigurable device. In the paper, several single-output zero-aliasing space compactors for a specific circuit under test ( CUT ) were generated in software, realized in the Java language, and were downloaded and tested at runtime in a simulation environment written in JBits.

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