Optimizing Power while Exploiting Fine Grain Parallelsim on FPGAs

T. Jiang, X. Tang, A. Jones, and P. Banerjee (USA)


Power optimization, IP core, PACT HDL compiler, FPGA


High-level design tools are needed to reduce the design time of complex chips consisting of millions of transistors. Such complex chips use a lot of fine grain parallelism to get high performance. With the rapidly advanced technology and the greatly increased integration density and clock frequency, power consumption is becoming more and more important. The PACT HDL compiler solves two problems: (1) it allows users to develop algorithms in a high level language, namely C, and synthesize hardware designs onto FPGAs while exploiting fine grain parallelism; (2) it explicitly addresses low power issues during the high-level synthesis stages. This paper presents an approach to optimize power while exploiting fine grain parallelism on FPGAs. We describe a high-level power optimization algorithm called ETAIP which is used in PACT HDL compiler with IP core binding methodology. By introducing the IP core library, both the flexibility and robustness of the design are improved. The ETAIP algorithm is capable of handling multi-cycle operators, and multi-cycle memory read and write operations. Experimental results are reported for the optimization algorithm on a benchmark suite of four signal and image processing kernels that are mapped onto the Xilinx XCV400 Virtex FPGA.

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