System Level Synthesis of Multiple IP Blocks in the Behavioral Synthesis Tool

R. Mukherjee, A. Jones, and P. Banerjee (USA)


System Level Synthesis, SOC, IP, C/C++, RTL VHDL


The trend to add ever more functionality onto systems on a chip (SOC), combined with the lack of automated design and verification tools, has resulted in excessive design times. One way to reduce the design times is with the use of pre-designed, pre-verified building blocks, called intellectual property (IP) blocks. The other way is to raise the design abstraction level and using system level or behavioral synthesis tools. While there are some known behavioral synthesis techniques for taking a given behavioral description of a single C function (one IP block) and generating an RTL representation, the techniques for automatically synthesizing a complex system having multiple IP blocks are not well known. This paper describes a system level approach for interfacing IP blocks that are automatically synthesized by a behavioral synthesis tool. We describe how the synthesis tool automatically creates ports and generates the required handshaking signals for interfacing the IP blocks in the system. Results of the system level synthesis and simulation are presented for single IP systems for streaming data and frame-based data, and for multiple IP blocks having streaming and frame-based data. 1

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