Hardware and Interface Synthesis of FPGA Blocks using Parallelizing Code Transformations

S. Gupta, M. Luthra, N. Dutt, R. Gupta, and A. Nicolau (USA)

Keywords

System synthesis, highlevel synthesis, interface synthesis, parallelizing transformations, FPGA, platform design

Abstract

Reconfigurable logic such as FPGAs is increasingly being used on system-on-chip (SoC) platforms to provide a flexible, programmable co-processor that augments the core processor. In this paper, we present a tightly coupled hardware synthesis and interface synthesis approach that forms part of our hardware-software co-design methodology for such FPGA-based platforms. For hardware synthesis, we use a parallelizing high-level synthesis approach that employs aggressive coarse-grain and fine-grain code parallelizing and code motion techniques to discover circuit optimization opportunities beyond what is possible with traditional high-level synthesis. We have implemented this approach in a framework called Spark that takes a behavioraldescription in ANSI-C as input and produces synthesizable register-transfer level VHDL. Our interface synthesis approach is based on a novel memory mapping algorithm that uses scheduling information from the high-level synthesis tool to map data used by both the hardware and the soft ware to shared memories on the reconfigurable fabric. We present experimental results for the synthesis of computationally intensive portions of multimedia applications that demonstrate that the code transformations in Spark lead to up to 50-70 % improvements in circuit delay with fairly constant circuit area. We also present a case study of the hardware-software co-design of a portion of multimedia application onto a FGPA platform using our methodology.

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