Reduced Variants of the Rijndael Cipher: Square Attack and Hardware Implementation

G.E. Mang (Romania)


Rijndael, encryption, HDL, square attack, hardwareimplementation


Reviewing the cryptanalysis of the five finalists for the Advanced Encryption Standard (AES), the National Institute of Standards and Technology (NIST) has decided to propose Rijndael as winner. In this paper we present a hardware implementation of a reduced version of the Rijndael algorithm using VHDL Hardware Description Language. For this implementation we use Xilinx Foundation 4.1 Software and VIRTEX XCV1000 board family. We chose this board for its characteristics: more than one million equivalent gates and 512 input/output buffers. In correlation with our implementation we extend the Square attack on Rijndael variants with larger keys of 192 bit and 256 bit. Our attacks exploit minor weaknesses of the Rijndael key schedule and are faster than exhaustive search for up to 7 rounds of the Rijndael cipher.

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