AES Candidate Algorithm Finalists: FPGA Implementation and Performance Evaluation

E. Mang, I. Mang, and C. Popescu (Romania)


Encryption, FPGA, Block cipher, VHDL, AES


The technical analysis used in determining which of the Advanced Encryption Standard candidates will be selected as the Advanced Encryption Algorithm includes efficiency testing of both hardware and software implementations of the candidate algorithms. Devices such as Field Programmable Gate Arrays (FPGAs) are highly attractive options for hardware implementations of encryption algorithms, as they provide cryptographic algorithm agility, physical security, and potentially much higher performance than software solutions. This contribution investigates the significance of FPGA imple mentttations of four of the Advanced Encryption Standard candidate algorithm finalists. Multiple architectural imple mentation options are explored for each algorithm. A strong focus is placed on high throughput implement tations, which are required to support security for current and future high bandwidth applications. The solutions will be compared in an effort to determine the most suitable candidate for hardware implementation within comer cially available FPGAs.

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