Sequential and Pipelined Architectures for AES Implementation

N.A. Saqib, F. Rodríguez-Henríquez, and A. Díaz-Pérez (Mexico)


Advanced Encryption Standard, cryptographic hardwarealgorithms, encryptor hardware cores, FPGAimplementations.


We present an efficient implementation of Rijndael cryptographic algorithm on FPGAs, new Advance Encryption Standard (AES). The implementation of AES has been made both in sequential and pipeline architectures and we are able to compare the results as an area-time tradeoff. Pipelined architecture reports higher performance at the cost of using more FPGA resources. In the sequential architecture, the design occupies 2744 CLB slices and achieved a throughput of 258.5 Mbits/s and there is no use of extra memory resources like FPGA BRAMs. On the other hand, our pipeline design occupies a total of 2136 CLB slices and achieved a throughput of 2868 Mbits/s. Both designs were realized on VirtexE family of devices (XCV812). The performance figures achieved by our implementations are not only efficient in terms of throughput but also the areas occupied by them are among the most economical reported up-to-date.

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