Computational Model and Architectural Proposal for a Hardware Type-2 Fuzzy System

M. Melgarejo (Columbia), C.A. Pea-Reyes (Switzerland), and A. Garca (Colombia)


Type-2 fuzzy logic, Type-2 fuzzy systems, fuzzy hardware, FPGA.


This paper presents an architectural proposal for a hardware based interval type-2 fuzzy inference system. It proposes a computational model which considers parallel inference processing and inner-outer bound sets-based type reduction. Taking into account this model, we conceived a hardware architecture for a type-2 fuzzy system with several pipeline stages for full parallel execution of fuzzy inferences. Distributed arithmetic is proposed for efficiently computing on hardware the type-reduction stage. The architectural proposal is used for specifying a type-2 fuzzy processor with reconfigurable rule base. It was synthesized and implemented onto two programmable logic devices.

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