Packet Scheduling in Proteo Network-on-Chip

D.A. Sigüenza Tortosa and J. Nurmi (Finland)


Network-on-Chip, Packet Scheduling, Network Simulation


This paper presents three different packet scheduling algo rithms specially suited for intra-chip packet-switching net works, called Networks-on-Chip (NoC), because of their simplicity. Their relative performance is evaluated in terms of total bandwidth, delay, delay jitter and fairness in the dis tribution of network resources. The system used for simu lation is a particular instance of our NoC proposal, called Proteo, which is briefly introduced. The simulation envi ronment is based on VHDL and Python. A brief study on the effects of local variation of scheduling parameters is in cluded. It is shown that it is possible to control bandwidth and delay in this way.

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