Low Power Tasks Mapping for DVS Capable Multiprocessor System with Shared Memory

M. Li, X. Wu, X. Zhu, and H. Wang (PRC)


Low Power, DVS, GA, ACO, System Level Synthesis


In the recent years, both voltage scheduling and low power system level synthesis have attracted substantial interest, but the integrated approach, which combines them to deliver the greatest potential, is still rarely touched. Meanwhile, most modern distributed systems are designed with both local memory and global memory units, but related models are still imprecise. In this paper, novel memory and energy aware models, which emphasize the local memory capacity constraint, memory occupation, variable lifetime and energy consumption, are presented; moreover, we present a novel low power tasks mapping method that exploits the two techniques on DVS capable distributed system with enough consideration on memory sub-systems. For a given architecture and a set of task graphs, tasks are assigned to different PEs using genetic algorithm, and then these partitioned task sets are transformed to a special graph, so that tasks scheduling and voltage scheduling are solved by a new meta-heuristic namely Cooperative Ant Colony Optimization.

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