Evaluation of Mechanisms Introduced to Improve Performance of TSVM Cache

A. Yamawaki and M. Iwane (Japan)


Cache Architecture, Communication, Synchronization, Shared Variable


The Tagged Shared Variable Memory (TSVM) is a con cept of the structured shared memory that combines com munication with synchronization to make parallel process ing more efficient. On a singlechip multiprocessor, the TSVM is realized by dividing a conventional data cache to two portions. The one is the TSVM cache and the other is a general variable cache. To achieve the maximum per formance gain, we introduce three methods to the physical TSVM. The first is to construct the dedicated bus for the physical TSVM. The second is to put the TSVM into the L1 data cache that each processor has. The third is to re lax the coherence maintenance for the TSVM cache. We evaluate in detail additional effects due to the above mech anisms using the simulator of a singlechip multiprocessor with the TSVM cache. The results show that construct ing the dedicated bus improves a performance of 0.01 to 38.38%, distributing TSVM cache achieves a performance gain of 2.10 to 34.34%, and relaxing the coherence mainte nance improves a performance of 3.55 to 24.08%. Conse quently, introduced three methods yield a total performance improvement of 10.54 to 77.38%.

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