An Accelerator Architecture for Programmable Multi-standard Baseband Processors

A. Nilsson, E. Tell, and D. Liu (Sweden)




Programmability will be increasingly important in future multi-standard radio systems. We are proposing an archi tecture for fully programmable baseband processing, based on a programmable DSP processor and a number of config urable accelerators which communicate via a configurable network. Acceleration of common cycle-consuming DSP jobs is necessary in order to manage wide-band modula tion schemes. In this paper we investigate which jobs are suitable for acceleration in a programmable baseband proc sessor supporting a number of common Wireless LAN and 3G standards. Simulations show that with the proposed set of accelerators, our architecture can support the discussed standards, including IEEE 802.11a 54 Mbit/s wireless LAN reception, at a clock frequency not exceeding 120 MHz.

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