Assembly Code Level Power Aware Optimization for Partitioned Memory Architectures

R. Levy, B. Narahari, and R. Simha (USA)


Power-aware, compiler, optimization, memory, energy


In this paper, we address the issues required to exploit power savings capabilities of partitioned memory systems. We present an assembly code-to-assembly code power-aware optimizer layer that extracts the existent relationships between code and data from the input assembly code, and suggest a variable placement in memory that can yield better power saving results. Given the final variable placement, the optimizer inserts the instructions required to control the power levels of the memory partitions directly into the input code, thereby generating a power-aware enhanced assembly output. An advantage of this approach is the complete independence of source code from the code being optimized, a feature which allows this optimization layer to be added to any compiler in order to explore power savings opportunities. This source code independence allows this technique to be applied to disassembled code for re-optimization. Additionally the proposed optimization is not limited to specific variable types such as scalar arrays, but can be applied to all variables in the input code.

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