Optimization for Instruction Level Parallelism by Adding, Spilling and Rematerialization

N. Ishii, K. Sumiyoshi, H. Ogi, and K. Iwata (Japan)


compiler optimization, spill code, rematerialization, soft ware pipelining


On the instruction-level parallel architecture such as VLIW, the performance is affected by the compiler technique. In this paper, we propose an integrated optimization technique which cooperates register reusing, spilling and rematerial ization First, we develop a register allocation method that can be decided, whether the register must be reusing or spilled or rematerialized by the prediction of the execution timing of the instruction in the program, when registers are insufficient. We evaluate our method in comparison with conventional compiler technique for blocks of programs. Second, the spilling and the rematerialization are also applied to the software pipelining to improve the paral lelism in the loops. It was shown that the spilling and the rematerialization adopted in the scheduling, improves the parallelism in the loop executions.

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