Multimedia Reconfigurable Hardware Design Space Exploration

E.M. Panainte, K. Bertels, and S. Vassiliadis (The Netherlands)


Design space exploration, reconfigurable architecture, mul timedia application, Molen programming paradigm


In this paper we consider a set of multimedia applications and investigate the potential performance impact a recon figurable microcoded processor can provide when added to a general purpose core processor. In a design space ex ploration, considering MPEG2 and JPEG benchmarks, we investigate performance boundaries, memory bottlenecks and the influence the core and reconfigurable processor communication has on performance. Under some realis tic scenarios and serial FPGA execution, it is shown that a 53 % cycle reduction is expected when comparing a design having a core processor and a design when the core pro cessor is augmented with a reconfigurable microcoded en gine. In addition, we have found that transferring parame ters between the core processor and the reconfigurable pro cessor may not severely influence the overall performance. Finally we investigated the memory bandwidth for opera tions mapped automatically on FPGA. The case study in dicates that small latency DCT hardware design performs well when interfaced with 512 bytes/cycle. Our studies also indicate that about 64 bytes/cycle will support high speed execution for SAD and IDCT.

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