Sizing Analog Circuits using an Improved Optimization-based Tool

P. Lakshmikanthan, S. Mulchandani, and A. Núñez (USA)


Analog Synthesis, Sizing, Automation, SPICE, GA, CAD


This paper presents a practical approach to improve the synthesis process of analog integrated circuits. It is based on embedding a set of analog design rules into a simulation-based synthesis tool. Unlike traditional simulation-based methods, embedded knowledge heuris tics guide the search engine towards an efficient solution in shorter execution times. No expert knowledge about the circuit is required as in the case of equation-based approaches, thereby eliminating the need for experienced analog designers. Our methodology is not restricted to any class of circuits, topologies, or fabrication process since the SPICE circuit simulator is used to evaluate the per formance. The corresponding simulation results are then used for evaluating circuit behavior. Results have been pro vided for extensively used analog circuits like the Folded Cascode Operational Transconductance Amplifier and the Two-Stage Comparator. These have been compared with results from other tools. For tight constraints, the proposed methodology has the ability to generate in short times, constraint-satisfying solutions which are difficult to obtain using pure simulation-based techniques.

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