A New Bit-Serial Multiplier Architecture for Area-Efficient FPGA Implementation

L. Morin, R. Beguenane, S. Simard, and É. Larouche (Canada)


Bit-serial, multiplier, parallel counter, area cost, FPGA.


This paper introduces an LSB-first bit-serial multiplier de sign which leads to area-reduced implementations in FPGA devices. Over the years, several bit-serial multiplier de signs have been investigated in the VLSI literature, mostly for high-frequency signal processing, but none of these de signs lead to very economic implementations when ported to FPGAs, and no FPGA-specific solution seems to have emerged until now. The proposed multiplier has the fol lowing characteristics: (1) it is area-efficient and suitable for FPGA implementations aimed towards compact real time DSP applications; (2) it receives serially two LSB first operands of arbitrary length; (3) it has the minimum latency a serial operator can have: it takes only one clock cycle before outputting the first bit of the product, and 2n clock cycles for a complete multiplication; (4) it contains sign-extension logic for performing signed multiplications; (5) for serially adding the partial products, it uses one sin gle parallel counter, carry adder, and carry register circuit; (6) it comparatively exhibits a moderate speed performance to existing designs.

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