Impact of Nanotechnology on the Performance of CMOS Digital Multipliers

D. Kudithipudi, R. Kotha, E. John, and Z. Pantic-Tanner (USA)


: Nanotechnology, Power, MultipliersI.


High performance multipliers are pivotal in the design of digital signal processors, multimedia applications and wireless communications. With the advent of nanotechnology, the requirements for low-power, high speed design has become imperative. In this paper, we have evaluated the effects of shrinking technology size (from 180nm to 70nm) on power, delay and power-delay product of multipliers, with increasing bit sizes. For all our simulations we used spice model parameters from Berkeley's Bsim3v3.Decreasing technology size from 180nm to 70nm has decreased the power by 36% in these multipliers. The latency has decreased by almost 50%. We have also computed a performance factor chart, which provides feasibility to choose the appropriate multiplier based on the nanotechnology. This table shows that, for a particular performance factor, optimal multiplier for one technology need not be optimal for a different technology size.

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