Compile-Time Energy Reduction Techniques based on Voltage Scaling Characteristic

T. Lei, X. Li, X. Hu, and X.-H. Zhou (PRC)

Keywords

Lowenergy software, compiler optimization, and voltagescaling characteristic

Abstract

The high power consumption of a processor is becoming a critical problem for both battery-powered devices and high performance computers. Any reductions in the operating frequency of the processor and its supply voltage can lead to significant savings in energy consumption (and heat dissipation) but cause longer execution times. In this paper, the problem of performance-lossless software energy reduction for variable-voltage processors is introduced based on the analysis of voltage scaling characteristic. We discuss compile-time energy reduction techniques which identifies voltage scaling opportunities to achieve energy savings without performance loss. The problem is formulated in terms of mixed integer linear programming formulation, which can sufficiently exploit the difference of voltage scaling characteristics of subtasks. The model can be built by using program profiling results or some necessary parameters, and the heuristic algorithm is presented. Experiment results demonstrate the effectiveness of our strategy by using known benchmark programs on a dedicated processor simulator. Finally the performance of the heuristic algorithm is studied and the impact of the transition overheads is analyzed as well.

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