Sequential Consistency Revisit: The Sufficient Condition and Method to Reason the Consistency Model of a Multiprocessor-on-a-Chip Architecture

Y. Zhang, W. Zhu, F. Chen, Z. Hu, and G.R. Gao (USA)


Sequential consistency, multiprocessor-on-a-chip, memory model


In his seminal paper in 1979 [1] on memory consistency, Lamport proposed two requirements for a multiprocessor system to be sequentially consistent. The second condition stated that memory "requests from all processors issued to an individual memory module are serviced from a single FIFO queue. Issuing a memory request consists of enter ing the request on this queue". Recently, the authors have the opportunity to revisit Lamport's conditions in the con text of a design study of the IBM Cyclops multiprocessor on-a-chip architecture (known as BG/C) from the system software angle. We find that when a multiprocessor system employs a network to communicate with its shared mem ory modules such as in the BG/C architecture - we need to carefully elaborate Lamport's requirements to cover the network. Thus we have refined the Lamport's second re quirement along this line and demonstrated that the revised conditions are sufficient for ensuring the sequentially con sistent behaviors for a class of BG/C-like architectures.

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