Noise Optimization and Design of PHS Front-End in CMOS

D. Feng and B. Shi (PRC)


Amplifier noise, LNA, mixer, noise optimization, and PHS.


Noise in CMOS low noise amplifier (LNA) is analyzed in detail, including channel noise and induced gate noise in MOS devices. A new analytical formula for noise figure is proposed including the effects of distributed gate resistance and intrinsic channel resistance. Power constrained noise optimization is performed. A design of CMOS PHS front-end using this technique is also included.

Important Links:

Go Back