Performance Evaluation of 3D-Interconnect Architectures for Network Line Cards

J. Engel and T. Kocak (USA)


Line cards, off-chip interconnect architecture, processor memory communications, k-ary n-cube networks, worm hole routing, packet processing


In this paper, we propose two off-chip interconnect archi tectures, called 3D-interconnects, to communicate between processing elements and memory modules located on net work line cards. The goal of the 3D-interconnect architec tures is to increase the throughput of the memory system since most currently deployed line card designs reach their maximum transfer rate. Moreover, line rates are constantly increasing while at the same time more data and function ality are embedded in each packet. The 3D-interconnect architectures allow multiple packet processing elements on a line card to access multiple memory modules. The nov elty of the proposed interconnects is their application and implementation as off-chip interconnects on the line card board. Our interconnects includes multiple, highly efficient techniques to route, switch, and control packet flows in or der to minimize congestion spots within the interconnects and packet loss. Performance results show that both inter connect designs achieve high throughput, low latency re sults surpassing other common interconnects currently de ployed. Moreover, the interconnects were able to sustain high traffic load while keeping low failure rates and high bandwidth utilization levels.

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