P. Raatikainen (Finland)
Broadband Communications, Modeling and Simulation, Switching, Dimensioning
High volume traffic presumes high-throughput routers that are connected together with high-speed links. Routers equipped with a number of high capacity links have to implement very powerful switch fabrics. Extending clock rates of a high performance switch fabric to line-cards leads to demanding electronics design and expensive line card implementations even in cases when only moderate link-speeds are supported. Hence, innovations that allow switch fabric interfaces to operate at clock rates lower than those inside the switch core are welcome. This paper analyzes the interface between a line-card and a switch fabric to find dimensioning rules that enable lowered bit rates while maintaining loss-free operation of the switch fabric.
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