A Width Expansion of MMX/SIMD Processing Architecture on an FPGA

R. Hoare, D. Swope, and S. Bailey (USA)


MMX, SIMD, Architecture, Multimedia, FPGA


Since its introduction on the Pentium Pro, MMX technology has increased the speed of processing by implementing a SIMD processing architecture using the existing floating point registers in the x86. This paper examines expanding the width of SIMD from 8 to 16, 32 and 64 processing elements of 8 bit operations by using three image benchmarks. The four hardware architectures were created using an FPGA as the target technology so that gate-level results could be measured. Post synthesis simulation was run and speedup is shown for all cases.

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