Hardware Scheduling in High-speed, High-capacity IP Routers

S.Q. Zheng, M. Yang, and F. Masetti (USA)

Keywords

MRMS problem, Multiserver switch architecture, Programmable kselector, Programmable prefix sums

Abstract

The key to the design of high speed, high capacity IP switches/routers with multiple servers in an input/output module is a fast scheduling scheme resolving input and output contentions. Such a scheduling scheme is a typical application of the multi requester, multi-server (MRMS) problem. To efficiently solve the MRMS problem and provide fair services to all requesters, we introduce four programmable k-selectors designs in this paper. Sim ulations on Altera’s CPLD (FPGA) demonstrate that our designs achieve significant performance improvement over the design using programmable priority encoders. Programmable k-selectors are very useful to construct hardware Request-Grant or Request Grant-Accept schedulers for high-speed, high-capacity multi-server switches/routers.

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