High Speed Routers Design using Reconfigurable Technology

A. El Kateeb and M. Gadde (USA)


Routers, cycleaccurate simulation, Reconfigurable technology, timing simulation


As the line rates standards are changing frequently to provide higher bit rates, the design of wire-speed router’s network processor unit has become very challenging. Typically, the design of new network processors is very costly and time consuming process. In this work, we are presenting a new approach that can be use in high-speed routers design. Our approach is to use a data stream distributor (or DSD) to split the high bit rate line to few lower rate lines. These low rate lines will be processed by existing network processors that are already in use with today low line rate routers. A cycle-accurate simulation is been investigated in this research to evaluate the functionality and performance of this new approach. The cycle’s accurate simulation has shown that the DSD approach can be used to split a 2.5 Gb/s line rate to four low bit rate lines of 622Mb/s. This approach has been evaluated by the use of reconfigurable chips such as Virtex from Xilinx.

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