Arbiter-free Counterflow Pipeline Processor: Designing Asynchronous Control Logic

V. Varshavksy (Israel) and V. Marakhovsky (Japan)


Counterflow Pipeline Processor, Asynchronous Control Circuit, Arbiterfree implementation, GALA approach to asynchronous design


The paper discusses developing asynchronous control log ics for Sproull’s Counterflow Pipeline Processor (CFPP) without the need for arbiters. As one can see, a syn chronous pipeline control circuit with two-track synchro nization is free from arbitration situations. One can build an asynchronous control circuit by a synchronous prototype using GALA-methodology and design of synchro-stratum which we suggested in our earlier papers.

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