Neural Network Approach to the Optimal LUT Assignment in FPGA for Parallel Multipliers over GF(2n)

T. Kurokawa (Japan)


Neural networks, parallel multipliers, finite field, minimum set covering problem, LUT, and FPGA


Parallel multipliers over GF(2n ) are often-used in cryptographic systems and error correction. Although it may be a time consuming operation, their special hardware design is necessary. This paper deals with their FPGA design using binary neural networks. As the structure of FPGA differs considerably from other integrated circuits, LUT in FPGA should be assigned efficiently for the reduction as well as the speeding up of the FPGA circuit. This LUT assignment problem can be classified as a kind of minimum set covering problem, which is a classical NP-complete problem. This paper proposes a binary neural network approach to solve this LUT assignment problem. For the design of parallel multiplier over GF(2n ), we prepare n neuron groups, each of which consists of binary neurons connected with each other using Hopfield type network. Following the architecture of the proposed binary neural network, parallel simulators are developed for simulation runs from GF(24 ) to GF(28 ). Their simulation results show that the proposed neural network can find out efficient LUT assignment methods in many cases to construct both smaller and faster circuits compared with other three representative parallel multipliers. Especially, its efficiency becomes the best when AT2 lower bounds are used.

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