A Power-Aware System Combining Static Compiling and DVFS

T. Chen, J. Qian, J. Huang, and Z. Zheng (PRC)


Power-aware system, DVFS, static compiler, memory, CPU.


Dynamic voltage and frequency scaling (DVFS) is an effective technique for controlling microprocessor energy and performance. We apply this technology on both CPU and memory. With the help of static compiler, we can divide the code to several segments. Scalability of the core frequency is a common feature of low-power processor architectures. Many heuristics for frequency scaling were proposed in the past to find the best trade-off between energy efficiency and computational performance. This paper presents a power-aware system combining the static compiler and DVFS. The obtained optimization system is deployed in a real hardware platform. This system concerns the power consumption of both memory and CPU. Experimental results, tested with different situation, show that significant energy savings are achieved with little performance degradation. With some good situations the energy savings can go up to about 10% (with little performance loss). The proposed technique is an effective method for voltage and frequency control of microprocessor and memory.

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