Minimizing Leakage: What if Every Gate Could Have Its Individual Threshold Voltage?

R. Salomon, F. Sill, and D. Timmermann (Germany)

Keywords

Genetic Algorithms, RealWorld Application, LowPower VLSI, Optimization

Abstract

Designers aim at fast but low-power consuming integrated circuits. Since high processing speed always comes with high energy demands, the literature provides several ways to reduce a circuit’s power dissipation. Even though tech nologically not possible today, this paper hypothesizes that the design would allow for choosing a gate’s from a con tinuous domain in order to explore options for future im provements. That is, the design goal consists in selecting a gate’s delay such that both the circuit’s delay and its power consumption assumes minimal values. Since the resulting optimization problem is multi-dimensional and might also contain local optima, this paper utilizes genetic algorithms for this task. On a selection of the well-known ISCACS test suite, the genetic algorithms reduced the circuits’ leakage values by about 20-50%; with respect to non-optimized circuits, the improvement is about 60-80%.

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