Write-Aware Buffer Cache Management Scheme for Nonvolatile RAM

K.H. Lee, I.H. Doh, J. Choi, D. Lee, and S.H. Noh (Korea)


Computer Architecture, NVRAM (Non Volatile RAM), Buffer Cache, Hit Ratio, Performance Metric


Nonvolatile RAM (NVRAM) technology is advancing rapidly with 1-2Mb capacity single-chip prototypes becoming available from major semiconductor companies. We will soon see NVRAM become an everyday component of our commodity computers. This paper explores the use of NVRAM as part of the buffer cache. A nonvolatile buffer cache provides a computer system with a means to maintain complete consistency as well as improved performance. The results of this paper can be summarized as follows. First, we show that the hit ratio that has been a commonly used metric to measure buffer cache performance is no longer adequate for caches with NVRAM. Instead of the hit ratio, we need to count the number of disk accesses to assess user perceived cache performance. Second, we show that because of this change in performance metric, when managing a buffer cache with NVRAM, one can do better than when using the MIN replacement algorithm mainly by distinguishing read and write operations. With this, we show that there is room for improvement in efficiently handling caches with NVRAM. Finally, based on these findings, we propose a simple and practical buffer management technique that improves on using the LRU algorithm.

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