Parallel On-Chip Ciphers Development for the Third Generation Mobile Telecommunication System

I.W. Damaj (Oman)


Hardware Design, Software Engineering, Parallel comput ing, Formal Models, Data Encryption, Gate Array


The paper focuses on the synthesis of a highly parallel hardware implementation of the main cipher designed for the third generation mobile communication system. The investigated algorithm is the KASUMI block cipher. Cur rently, KASUMI is well known to be a strong encryption al gorithm. The use of such an algorithm within critical appli cations, such as mobile communication, requires efficient, highly reliable and correct hardware implementation. We will investigate satisfying such requirements by proposing and adopting a step-wise refinement software engineering approach to develop correct hardware circuits. The method uses a formal functional programming notation for spec ifying algorithms. The parallel behavior is then obtained through the use of a combination of function decomposi tion strategies, besides, data and process refinement tech niques. The refinements are inspired by the operators of Communicating Sequential Processes (CSP) and map eas ily to programs in Handel-C (a modern C-based high-level langauge with hardware output). In this paper, we ob tain several hardware implementations with different per formance characteristics by applying different refinements to the algorithm. The developed designs are compiled and tested under Celoxica’s RC-1000 reconfigurable computer with its 2 million gates Virtex-E FPGA. Performance anal ysis and evaluation of these implementations are included.

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