A High-Performance Low-Power Ethernet Controller with Embedded 8-Bit MCU for Information Appliances

Z. Zheng, X. Zou, L. Zou (PRC), and H. Gang (Canada)

Keywords

SoC, MAC, PingPong FIFO, Circular buffer, Throughput

Abstract

In this paper, an Ethernet controller System-on-Chip (SoC) solution for information appliances is presented. Integrated on a single chip, it includes an enhanced one cycle 8-bit MCU, a high-performance Media Access Controller, 32-kB ROM for BootLoader,32-kB SRAM for data buffer, 128-kB flash memory for firmware, and ample peripheral blocks. In order to achieve high performance, the embedded 8-bit 8051 MCU is optimized by independent instruction bus and data bus. Besides, a two-stage pipeline feature is added. Compared with the existing 8051 core, the enhanced one-cycle MCU offers ten times improvement in instruction execution efficiency. Meanwhile, the performance of MAC is greatly improved by adopting various techniques such as DMA that all increase the data transfer rate. In order to reduce the power consumption greatly, multiple working clocks are used according to different circuits. Moreover, in order to achieve rapid data communication in different working clock frequencies’ circuits, a simple ping-pong FIFO circuit is realized. The chip is implemented using TSMC 0.25-µm two-poly four-metal mixed signal CMOS technology. Its die area is 4.8×4.578mm2. Test results show that the maximum throughput of Ethernet packets can reach 7Mbps while the power consumption is rather low the working current is just about 200mA.

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