Design of Four-Valued Memory using Three-Peak MOS-HBT-NDR Circuits

K.-J. Gan, D.-S. Liang, C.-S. Tsai, C.-M. Wen, Y.-Z. Lin, and T.-C. Chang (Taiwan)

Keywords

Negativedifferentialresistance (NDR), heterojunction bipolartransistor (HBT), metaloxidesemiconductor fieldeffecttransistor (MOS), Λtype, Ntype.

Abstract

A four-valued memory circuit based on three-peak MOS-HBT-NDR circuit is investigated. The MOS-HBT NDR circuit is made of metal-oxide-semiconductor field effect-transistor (MOS) and heterojunction-bipolar transistor (HBT) devices. However it can show the negative-differential-resistance (NDR) current-voltage characteristic by suitably arranging the MOS parameters. The four-valued memory circuit is constructed by a three paralleled-connected MOS-HBT-NDR circuit as the driver and a resistor as the load. The simulation is based on the standard 0.35µm SiGe process.

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